HDLbits

Getting started

(1) Getting Started

module top_module( output one );

// Insert your code here
    assign one = 1;

endmodule

(2) Zero

module top_module(
    output zero
);// Module body starts after semicolon

endmodule

Verilog language

(1) Wire

module top_module( input in, output out );
    assign out = in;

endmodule

(2) Wire4

module top_module( 
    input a,b,c,
    output w,x,y,z );

    assign {w, x, y, z} = {a, b, b, c};

endmodule

(3) Notgate

module top_module( input in, output out );
    assign out = ~in;

endmodule

(4) Andgate

module top_module( 
    input a, 
    input b, 
    output out );

    assign out = a & b;

endmodule

(5) Norgate

module top_module( 
    input a, 
    input b, 
    output out );

    assign out = ~(a|b);

endmodule